1. Field
The present disclosure generally relates to integrated circuits (ICs). More specifically, aspects of the present disclosure relate to a volatile memory and a one-time program (OTP) compatible memory cell and programming method.
2. Background
Semiconductor memory devices include, for example, a static random access memory (SRAM) and a dynamic random access memory (DRAM). A DRAM memory cell generally includes one transistor and one capacitor, thereby providing a high degree of integration. DRAM, however, uses constant refreshing, which limits the use of DRAM to computer main memory. An SRAM cell, by contrast, is bi-stable, meaning that it can maintain its state indefinitely, so long as adequate power is supplied. SRAM also supports high speed operation, with lower power dissipation, which is useful for computer cache memory.
One example of an SRAM cell is a six transistor (6T) SRAM cell that includes six metal-oxide-semiconductor (MOS) transistors. The core of an SRAM cell may be formed by using two cross-coupled inverters. The two inverters are connected using a feedback loop in which the output potential of each inverter (e.g., Vout) is fed as input to the other inverter (e.g., Vin). The cross-coupling of the inverters using the feedback loop stabilizes the inverters to their respective state.
One advantage of SRAM cells is their ability to handle external direct current (DC) noise. The capability of an SRAM cell to handle external DC noise is based on the static noise margin (SNM) of the SRAM cell. The SNM of an SRAM cell is determined by nesting the largest possible square in the two voltage transfer curves (VTC) of the inverters. The SNM of the SRAM cell may be defined as the side-length arranged between the VTCs of the inverters. Unfortunately, when external DC noise exceeds the SNM of an SRAM cell, the state of the SRAM cell changes, resulting in a loss of the stored data.